PCI Express pumps up performance

In the past decade, PCI has served as the dominant I/O architecture for PCs and servers, carrying data generated by microprocessors, network adapters, graphics cards and other subsystems to which it is connected. However, as the speed and capabilities of computing components increase, PCI’s bandwidth limitations and the inefficiencies of its parallel architecture increasingly have become bottlenecks to system performance.

PCI is a unidirectional parallel bus architecture in which multiple adapters must contend for available bus bandwidth. Although performance of the PCI interface has been improved over the years, problems with signal skew (when bits of data arrive at their destination too late), signal routing and the inability to lower the voltage or increase the frequency, strongly indicate that the architecture is running out of steam. Additional attempts to improve its performance would be costly and impractical. In response, a group of vendors, including some of the largest and most successful system developers in the industry, unveiled an I/O architecture dubbed PCI Express (initially called Third Generation I/O, or 3GIO).

PCI Express is a point-to-point switching architecture that creates high-speed, bidirectional links between a CPU and system I/O (the switch is connected to the CPU by a host bridge). Each of these links can encompass one or more “l(fā)anes”comprising four wires——two for transmitting data and two for receiving data. The design of these lanes enables the use of lower voltages (resulting in lower power usage), reduces electromagnetic emissions, eliminates signal skew, lowers costs through simpler design and generally improves performance.

In its initial implementation, PCI Express can yield transfer speeds of 2.5G bit/sec in each direction, on each lane. By contrast, the version of the PCI architecture that is most common today, PCI-X 1.0, offers 1G bit/sec in throughput. PCI Express cards are available in four- or eight-lane configurations (called x4 and x8). An x4 PCI Express card can provide as much as 20G bit/sec in throughput, while an x8 PCI Express card can offer up to 40G bit/sec in throughput.

Earlier attempts to create a new PCI architecture failed in part because they required so many changes to the system and application software. Drivers, utilities and management applications all would have to be rewritten. PCI Express developers removed the dependency on new operating system support, letting PCI-compatible drivers and applications run unchanged on PCI Express hardware.

A bus for the future

Developers are working on increasing the scalability of PCI Express. While current server and desktop systems support PCI Express adapters and graphics cards with up to eight lanes (x8), the architecture will support as many as 32 lanes (x32) in the future.

The first Fibre Channel host bus adapters were designed to support four lanes instead of eight lanes, in part because server developers had designed their systems with four-lane slots. As even more bandwidth is required, implementing an eight-lane design potentially could double the performance, provided there were no other bottlenecks in the system.

This scalability, along with the expected doubling of the speed of each lane to 5G bit/sec, should keep PCI Express a viable solution for designers for the foreseeable future.

PCI Express is a significant improvement over PCI and is well on its way to becoming the new standard for PCs, servers and more. Not only can it lower costs and improve reliability, but it also significantly can improve performance. Applications such as music and videostreaming, video on demand, VoIP and data storage will benefit from these improvements.

PCI Express總線提升性能

在過去十年間，PCI總線一直是PC機(jī)和服務(wù)器上的主流I/O架構(gòu)，它負(fù)責(zé)將微處理器、網(wǎng)卡、圖形卡和其他子系統(tǒng)生成的數(shù)據(jù)送到與它相連的部件。然而，隨著計(jì)算部件的速度和能力的提高，PCI并行架構(gòu)的帶寬局限性和低效率越來越成為系統(tǒng)性能的瓶頸。

PCI是一個單向的并行總線架構(gòu)，其中多個適配器必須爭奪可用的總線帶寬。雖然PCI接口的性能幾年來不斷得到改進(jìn)，但信號偏離(數(shù)據(jù)位到達(dá)目的地太晚)、信號路由、以及電壓無法降低或頻率更高時(shí)就不能正常工作等問題，無不表明該架構(gòu)走到了盡頭。改進(jìn)其性能的設(shè)想代價(jià)很高，也不實(shí)際。針對此問題，一些廠商(包括最大的和最成功的系統(tǒng)開發(fā)商)公布了一個叫PCI Express(最初叫第三代I/O，縮寫為3GIO)的I/O架構(gòu)。

PCI Express是一個點(diǎn)對點(diǎn)的交換架構(gòu)，在CPU和系統(tǒng)I/O之間建立高速的雙向鏈路(交換機(jī)由主橋接到CPU)。每一個鏈路可以包含一個或多個由四條電線組成的“通道”，其中兩條線發(fā)送數(shù)據(jù)，兩條線接收數(shù)據(jù)。這些通道的設(shè)計(jì)能允許在低壓下使用(這樣功率消耗較少)、降低電磁輻射、消除信號偏離、以及簡化設(shè)計(jì)帶來的成本降低，總的來說改進(jìn)了性能。

在其最初的實(shí)現(xiàn)中，PCI Express就能保證在每個通道上雙向的傳輸速度達(dá)到2.5G位/秒。而目前最常見的PCI架構(gòu)版本——PCI-X 1.0提供的吞吐量為1G 位/秒。目前能得到的PCI Express卡為4通道或8通道的配置(叫x4和x8)。x4 PCI Express卡能提供的吞吐量達(dá)到20G 位/秒，而x8 PCI Express卡能提供的吞吐量則高達(dá)40G 位/秒。

早期創(chuàng)建新的PCI架構(gòu)的設(shè)想之所以失敗了，是因?yàn)橐笙到y(tǒng)和應(yīng)用軟件做太多的修改，驅(qū)動程序、例行程序和管理應(yīng)用程序全都必須重寫。PCI Express開發(fā)者消除了對新操作系統(tǒng)支持的依賴，讓與PCI兼容的驅(qū)動程序和應(yīng)用程序無需更改就能在PCI Express硬件上運(yùn)行。

未來的總線

目前，開發(fā)者正在研究如何提高PCI Express的可擴(kuò)展性?，F(xiàn)在的服務(wù)器和臺式系統(tǒng)支持多達(dá)8通道(x8)的PCI Express卡和圖形卡，而將來該架構(gòu)能支持多達(dá)32通道(x32)。

第一個光纖通道的主總線適配器設(shè)計(jì)成支持4通道，不是8通道，部分原因是由于服務(wù)器開發(fā)商已經(jīng)將其系統(tǒng)設(shè)計(jì)了4通道插槽。當(dāng)需要更多帶寬時(shí)，實(shí)現(xiàn)8通道的設(shè)計(jì)能使性能翻一番，只要系統(tǒng)中沒有其他的瓶頸。

此可擴(kuò)展性加上每個通道的速度有望加倍，達(dá)到5G位/秒，應(yīng)該可以使PCI Express在可預(yù)計(jì)的未來成為設(shè)計(jì)師可用的選擇方案。

PCI Express相對PCI是一次重大的改進(jìn)，它正在沿著成為PC機(jī)、服務(wù)器以及更多設(shè)備新標(biāo)準(zhǔn)的道路前進(jìn)。它不僅降低了成本、提高可靠性，而且還能顯著地改善性能。音樂和視頻流、視頻點(diǎn)播、網(wǎng)絡(luò)電話和數(shù)據(jù)存儲等應(yīng)用程序也將從這些改進(jìn)中受益。