計算機選讀(960)

Over the years, the clock frequency became the key measure of processor performance. In parallel with Moore's Law, which predicts that the number of transistors on a chip increases exponentially, the clock frequency has done the same, doubling roughly every 18 months from thousands of ticks per second in 1977, to millions in the 1980s, to billions today. But while optimists believe that this process will continue, chip developers across the industry now agree that clock frequency will no longer be the key metric of processor performance, for several reasons.

The first is the growth of parallelism——the practice of getting a chip to execute many different operations simultaneously. In the past, this was confined to the realm of high-end supercomputers, as a way of improving their performance. But it is now becoming common in personal computers, and is bound to become more so.

A driving factor behind this parallelism is the fact that, while processor speed has increased with such remarkable rapidity, the speed of memories has lagged. What's more, the gap between processor speed and memory speed is likely to grow. Parallelism within a single chip allows several different processing units to share the same memory, so the memory's slowness is not such a problem.

This is because the limiting factor is not so much the throughput of memory chips (the rate at which data can be moved in and out of them) but the administrative overhead associated with moving information in and out of the processor. Because of this, chip designers can gain by putting several distinct processors on the same chip, and have them share a fast, local memory inside the chip itself. This approach is known as multiple cores, or multi-core for short. A related approach is known as simultaneous multi-threading. It involves modifying a single processor to enable it to switch quickly between several distinct tasks. While one task is waiting for data to arrive from the main memory, another can continue to execute——so a single processor can in effect, do the work of many.

A second reason why clock frequency will no longer be an accurate measure of performance is that distributing the clock's signal to all the different parts of a chip is more difficult that it sounds. Reducing the “skew” on a chip ——the amount by which clock signals might be out of synch——takes a very skillful chip designer. It is becoming more difficult as chips get larger and more complex.

That's why “asynchronous” technology is exploring aggressively, which involves getting rid of the clock entirely. This approach has costs and benefits, since miniature circuits known as “rendezvous circuits” must be placed at circuit junctions to co-ordinate the flow of data. It is rather like replacing a city-wide network of traffic lights with policemen at every corner. In one recent experiment with a test chip that could run in both synchronous and asynchronous modes, the asynchronous mode won out. That's because in a synchronous design, every operation must wait for the slowest one to complete, while in an asynchronous one, a laggard only delays the local part of calculation.

Clockless chips also have the added benefit of emitting for less radio interference. So asynchronous circuits could be particularly useful in devices such as mobile phones, where radio interference is a substantial concern.

Finally, getting chips to run at higher clock frequency is diminishing in importance because another problem is becoming more pressing: getting them to consume less power.. Power consumption is now the biggest problem in chip design.

速度不是一切

多年來，時鐘頻率一直是處理器性能的主要測量指標。與預測芯片上晶體管數(shù)目指數(shù)地急劇增加的摩爾定律相輔相成，時鐘頻率也是做同樣的事，每18個月翻一番，從1977年的每秒幾千次，增加到上個世紀80年代的幾百萬次，到目前的幾十億次。雖然樂觀主義者還認為這個過程將繼續(xù)，但是全行業(yè)的芯片開發(fā)人員都同意，時鐘頻率因多種原因將不再是處理器性能的主要指標。

首先是并行處理的發(fā)展——讓芯片同時執(zhí)行很多不同操作的做法。過去，并行處理僅限于高端的巨型機，作為提高性能的方法。但現(xiàn)在，它在個人計算機中也已常見，而且會越來越多。

并行處理背后的驅動因素是這樣一個事實，當處理器的速度快速提高的同時，存儲器的速度卻落后了。更有甚者，處理器速度與存儲器速度之間的差距有可能拉大。單一芯片中的并行性讓幾個不同的處理器共享同一存儲器，從而存儲器的緩慢不再是一個問題。

這是因為很大程度上限制因素不是存儲器芯片的吞吐能力(數(shù)據(jù)進出存儲器的速率)，而是與信息出入處理器相關聯(lián)的管理開銷。正由于此原因，芯片設計師能做到在同一芯片中放入多個處理器并共享該芯片內的快速本地存儲器。該方法叫做多內核。另一個相關的方法叫同時多線程。它涉及到改進單一處理器，使之能在幾個不同的任務之間快速轉換。當一個任務等待主存中的數(shù)據(jù)送來之時，另一個任務能繼續(xù)執(zhí)行——從而單個處理器實際上能做很多工作。

時鐘頻率不再是性能的精確測量指標的第二個原因是，將時鐘信號分配到芯片的不同部分，要比說說困難得多。減少芯片上的“偏差”——時鐘信號失去同步的程度，需要技術高超的芯片設計師。隨著芯片越來越大、越來越復雜，這個問題也變得更加困難。

這就是為什么“異步”技術得到大力研究開發(fā)，該技術涉及到將時鐘徹底去除。此方法既有得也有失，因為必須在電路交接點放置稱之為“聚集電路”的微型化芯片，以協(xié)調數(shù)據(jù)的流動。這相當于在每個路口用警察代替整個城市的交通信號燈網絡。在最近的一次對測試芯片(在同步和異步方式下都能運行)進行的實驗中，異步方式勝出。這是因為在同步設計中每個操作必須等待最慢操作的完成，而在異步方式下遲緩的操作只是延緩局部的計算。

無時鐘的芯片還有一個額外的優(yōu)點，即輻射更少的射頻干擾。因而異步電路特別適合用于移動電話等對射頻干擾非常關注的設備。

最后，讓芯片運行在更高時鐘頻率的重要性也在減小，因為另一個問題變得更為迫切：讓(芯片)消耗更少的電能。能耗現(xiàn)已是芯片設計中最大的問題。